OpenPOWER-HDL-Cores -- An open ML for discussing all matters related to HDL/Software implementation of OpenPOWER compliant CPU cores, SoCs, FPGAs etc.


About OpenPOWER-HDL-Cores
English (USA)

A community mailing list for discussing OpenPOWER CPUs written in a HDL (VHDL, Verilog, NMigen etc.) that can in turn be run in a simulator or instantiated on a FPGA, ASIC etc.

List participants are asked to conduct themselves in a courteous manner. List moderators retain the right to moderate posts or in extreme cases unsubscribe participants.

To see the collection of prior postings to the list, visit the OpenPOWER-HDL-Cores Archives.

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