[OpenPOWER-HDL-Cores] introducing libre-soc: nmigen hybrid cpu-vpu-gpu

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Mar 28 22:10:55 UTC 2020


http://bugs.libre-riscv.org/show_bug.cgi?id=269
https://libre-riscv.org/openpower/isa/

began manually extracting the pseudo-code segments based on PDF to TXT
conversion.  there's a few niggles (use of ellipsis,
pseudo-code-fragments missing for CA, CA32, CR0, OV etc. ) however as
a general rule it's pretty good.

second phase will be writing a BNF parser (probably python-ply) that
"understands" the pseudo-code format and outputs what we want.

IEEE754 FP is a little more problematic as almost all of it is in "words".

l.


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