[OpenPOWER-HDL-Cores] RADIX MMU in microwatt

lkcl luke.leighton at gmail.com
Thu Apr 1 20:26:55 UTC 2021


https://github.com/antonblanchard/microwatt/blob/master/mmu.vhdl
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/isa/radixmmu.py;hb=HEAD

we're implementing the microwatt RADIX MMU in the python-based simulator so
that we can do single-step comparisons of LibreSOC (and microwatt, later).

we're having some difficulty determining how it works, given that it is a
FSM that jumps to different locations.  in particular we are unable to
determine what SEGMENT_CHECK is for, and what checking the top bit of the
address is meant to do, when selecting pte0 or 3.

this *should* be identical to power-gem5 radixmmu but is not, because they
implemented hypervisor in full.

is there some resource around which could help us work out the sequence of
events, or could someone kindly help review radixmmu.py above?

l.
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