[OpenPOWER-HDL-Cores] single and twin-predication added to python-based LibreSOC simulator

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Mar 17 22:36:06 UTC 2021


https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/isa/test_caller_svp64_predication.py;h=cd4df1e929d4c6250139e61840339ed19e2e7b02;hb=HEAD#l45

to be followed up in HDL over the next couple of weeks, the above
successful unit test illustrates how twin-predication works.
single-predication is just below, and includes both an INT (GPR) mask
as well as a CR-Field mask unit test.

"normal" Vector ISAs only have single-predication.  every element in
source and dest of the vector matches up:
   for i in range(VL):
        if mask & (1<<i):
             Vector_Operation_Proceeds()

SVP64 for operations that have only one source and one destination are
permitted *two* masks: one for the source element, one for the
destination (including LD/ST after EA is computed).  this is
effectively a back-to-back VREDUCE-VEXPAND except it takes place on
*operations* not just MVs.  fsqrt, extsw, popcnt - everything and
anything that's a single-src, single-dest.

l.

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