[OpenPOWER-HDL-Cores] SVP64 auto-generated table for microwatt decoding

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Mar 18 12:48:51 UTC 2021


i've updated the microwatt auto-generated sv_decode.vhdl file with two things:

1) the RS field is now back in "in3" (we moved it to "in1" in LibreSOC)

1) a new "out2" column and corresponding "sv_out2" column has been added

the sv_out2 column is critically important, and the "out2" column was
implicitly added by "is this a LD/ST-with-update" instruction, which
is hard-coded in microwatt.  with that missing, it wasn't possible to
auto-generate the corresponding sv_out2 column.

each of the columns sv_in* and sv_out* as well as the CR field versions all say:

"for this openpower v3.0B instruction, if you want to know which bits
of the SVP64 Re-Map to get the "EXTRA" information (whether the
register is Vectorised), go to THIS part of the field".

        -- insn  Ptype  Etype  in1  in2  in3  out  out2  CR in  CR out
 sv_in1  sv_in2  sv_in3  sv_out  sv_out2  sv_cr_in  sv_cr_out
                0 => (P2, EXTRA3, RA_OR_ZERO, NONE, NONE, RT, NONE,
NONE, NONE, Idx1, NONE, NONE, Idx0, NONE, NONE, NONE), -- ld
                2 => (P2, EXTRA3, RA_OR_ZERO, NONE, NONE, RT, NONE,
NONE, NONE, Idx1, NONE, NONE, Idx0, NONE, NONE, NONE), -- lwa
                1 => (P2, EXTRA2, RA_OR_ZERO, NONE, NONE, RT, RA,
NONE, NONE, Idx2, NONE, NONE, Idx0, Idx1, NONE, NONE), -- ldu

here you can see for ldu:

* out=RT
* out2=RA (LD-with-update)

and that:

* sv_out=Idx0 and
* sv_out2=Idx1

this means, "if you want to know if RA - as the 2nd output - has been
Vectorised and altered to be *different* from RA-as-a-src, please look
in EXTRA field Indexed 1"

the "normal" v3.1 64-bit prefixing system actually has bits in it
which tell you what to do.  unfortunately, we have so little space
that we can't do that, and consequently it's the decode1.vhdl which
has to be extended on a per-operation basis.

l.


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