[OpenPOWER-HDL-Cores] review of v3.1 new bitmanip logical operations not Rc=1
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sat Mar 20 13:44:55 UTC 2021
folks there are some discrepancies in v3.1 page 105, all of them do not
have the option to respect Rc=1.
cntldzm i would expect, like its non-mask counterpart, to have an Rc=1
variant because at the very least knowing that the result is zero is useful.
centrifuge likewise i would expect it to be useful to know if the MSB was
zero, which is the CR "gt" bit (something like that).
pextd and pdepd a combination of both is useful: knowing if the result is
zero and if the MSB is zero.
was this an oversight or were there ISA design issues that led to an
explicit decision to exclude Rc=1?
if it was an oversight how may this be corrected?
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the OpenPOWER-HDL-Cores