[OpenPOWER-HDL-Cores] microwatt / libresoc dcache
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu May 6 19:24:28 UTC 2021
allo again paul,
for reference here is dcache.py:
pretty much near-identical to dcache.vhdl, one major difference: the bottom
3 LSBs of the address are *not* copied onto the WB bus (as previously
discussed, a 32 bit address @ 64 bits wide data must put *29* MSBs onto the
WB Bus, *not* the full 32)
appreciated the input yesterday about dcache.vhdl, the 3 cycles:
* AGEN (address generation)
* ST data drop
* actual fetch.
so this is where it gets interesting: we also have an AGEN Phase in
Libre-SOC, but because the intent is to be an Out-of-Order design plus also
to allow single regfile read port thru triple read ports as a config
option, we have *no idea* if the two RA / RB regs for AGEN will come before
*or after* the RS from a STORE operation!
therefore i had to stall the introduction of the AGEN assertion into
dcache.py until the ST reg has been read (many cycles later, at present).
c'est la vie :)
my question to you is about the cache sram reading (not writing)
here you can see ADR_BUF=true, and it is set in dcache.py
a normal SRAM you would expect a 1 clock cycle delay, all good. except
here, an *extra* cycle of delay is added. after assertion of the read it
is *two* cycles before the data appears on the read data output.
i have no idea why, and i'm not skilled enough at VHDL to work out how to
any chance of making that a config-selectable option in dcache.vhdl? i can
then see how that was done and make corresponding edits.
it is not a high priority, the code is "functional" as-is.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the OpenPOWER-HDL-Cores