[OpenPOWER-HDL-Cores] [Libre-soc-dev] microwatt / libresoc dcache
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri May 7 10:14:52 UTC 2021
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Fri, May 7, 2021 at 6:47 AM Paul Mackerras <paulus at ozlabs.org> wrote:
> On Fri, May 07, 2021 at 05:17:44AM +0100, Luke Kenneth Casson Leighton wrote:
> > clk rise fall rise fall rise fall
> > rd_in: 1 0 0 0 0 0
> Do you mean rd_en?
yes, sorry. late night. errr, early morning.
> The other point, which you don't seem to have taken in yet, is that
> this is NOT the critical path.
i've not yet closely examined the virt path, for this analysis.
> > essentially, i am questioning why ADD_BUF was added.
> To match the latency of the path to the way multiplexer data inputs
> with the latency to the way multiplexer address inputs (the way
> multiplexer is the statement "data_out := cache_out(r1.hit_way);").
oh hang on... the address is asserted a cycle early, isn't it?
arrgh, that means that the ADD_BUF is needed to get the
data to "catch up" with the rest of the code.
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