[OpenPOWER-HDL-Cores] microwatt / libresoc dcache

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat May 8 11:59:09 UTC 2021


On Saturday, May 8, 2021, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

>
> solutions that i have seen to this, used by intel, have been to make
> multi-level
> PTE caches. an 8-entry single-cycle, followed by (guessing) 256-entry
> two-cycle
> followed by (guessing) 4k three-cycle.


https://github.com/lowRISC/ariane/blob/master/src/tlb.sv

ariane only has four entry TLB caches!  this seems to be enough, and is
small enough to do in 1 clock cycle.

also interestingly they cache how far down the RADIX the lookup went.
RISC-V hardcodes the page table sizes to 4k, 2M and 1G.

whereas POWER allows the OS to define them, making a TLB cache design a
leetle more fun.

l.




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