[OpenPOWER-HDL-Cores] microwatt / libresoc dcache

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat May 8 14:30:08 UTC 2021


-- L1 DTLB entries per set
TLB_SET_SIZE : positive := 64;

oof, that's a hell of a lot, paul :)  that's a 64-entry CAM, what...
48 bits of address-compares?  48x XOR gates (10 gates per XOR), times
64, that's 31,000 gates!  woo!


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