[OpenPOWER-HDL-Cores] Fwd: [Libre-soc-dev] ISA analysis

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun May 9 10:51:08 UTC 2021

i'm forwarding this to openpower-hdl-cores in lieu of the ISA WG
discussion forum being established, because the analysis carried out
looks to be deeply impressive, the entire paper is well worth reading
for snippets such as the one below.

in the case of LD/ST they actually added built-in shift by 32 in the
AGEN phase, and they may also have added it as LD/ST-with-update as
well.  i'm always on the lookout for insights like this so have
recorded it here

---------- Forwarded message ---------
From: Lauri Kasanen <cand at gmx.com>
Date: Sun, May 9, 2021 at 6:18 AM
Subject: Re: [Libre-soc-dev] ISA analysis
To: <libre-soc-dev at lists.libre-soc.org>

On Sun, 9 May 2021 00:10:34 +0100
Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:

> https://news.ycombinator.com/item?id=24459314
> fascinating.  particularly that the alibaba team had to add custom
> addressing modes to RISCV in order to achieve decent performance.

For reference:

First, we support register + register addressing mode, and
support indexed load and store instructions. This type of
instruction extension reduces the usage of the registers for
calculation and reduces the number of instructions for address
generation, thereby effectively accelerating the data access
of a loop body. Second, unsigned extension during address
generation is supported. Otherwise, the basic instruction set
does not support direct unsigned extension from 32-bit data
to 64-bit data, resulting in too many shift instructions.

So not x86's "add this and multiply that"
address-struct-member-in-an-array-of-structs addressing after all.

- Lauri

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