[OpenPOWER-HDL-Cores] u-boot for openpower

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon May 10 12:30:59 UTC 2021


allo Ben, been a while, nice to hear from you.

On Monday, May 10, 2021, Benjamin Herrenschmidt <benh at kernel.crashing.org>
wrote:

>
> We are familiar with u-boot and bare metal initializations. The problem
> here is that sdram_init is partially auto-generated and based on
> whatever changes are happening in LiteX upstream which is still quite a
> moving target.


ahh got it.


>
>
> It would probably be nicer if LiteDRAM inits could be refactored in a
> more data-driven way such that some kind of very compact table gets
> stored in a block "ROM" in the FPGA and a slightly more generic init
> code follows it.


 yes, agreed.  of course, the difference between FPGA and ASIC, the
assumption of FPGA is, "well you can always re-run the build target
command".

and in litex you specify which DRAM IC is connected as a compile-time
option.

with the autogeneration logic already being in place, what you suggest
should be a straightforward (albeit quite extensive) code-morph exercise.
i.e. the selection of DRAM ICs is entirely dynamic (in python) so morphing
to a different type of dynamic selection where that python is translated to
c to read the ROM, i get the idea and think it's quite sensible.

l.



-- 
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