[OpenPOWER-HDL-Cores] microwatt / libresoc dcache

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue May 11 12:06:04 UTC 2021


https://ars.els-cdn.com/content/image/3-s2.0-B978012800056400008X-f08-09-9780128000564.jpg

i know where i got the impression that TLBs are a CAM from: see the bottom
left of the image? that's a classic circuit for a CAM.  multiple compares
(XORs) plus MUX-en plus OR cascade.

interestingly it is the *way* (column) that is the CAM, not the set (row).

i am still not seeing where the inefficiency (gate delay) comes from.  the
only possibility i can think of, the rows contain *all* ways then index
them as a Shift Register.

i would have done the organisation of the TLB a little differently: 4 ways
==> 4 separate 64 bit straight linear SRAMs of 64 entries each, rather than
64 entries with 4x64 bits in each row.

was there a reason why it wasn't done that way?

l.


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