[OpenPOWER-HDL-Cores] microwatt / libresoc dcache

Benjamin Herrenschmidt benh at kernel.crashing.org
Tue May 11 21:55:23 UTC 2021


On Tue, 2021-05-11 at 13:06 +0100, Luke Kenneth Casson Leighton wrote:
> https://ars.els-cdn.com/content/image/3-s2.0-B978012800056400008X-f08-09-9780128000564.jpg
> 
> i know where i got the impression that TLBs are a CAM from: see the
> bottom left of the image? that's a classic circuit for a CAM. 
> multiple compares (XORs) plus MUX-en plus OR cascade.
> 
> interestingly it is the *way* (column) that is the CAM, not the set
> (row).
> 
> i am still not seeing where the inefficiency (gate delay) comes
> from.  the only possibility i can think of, the rows contain *all*
> ways then index them as a Shift Register.
> 
> i would have done the organisation of the TLB a little differently: 4
> ways ==> 4 separate 64 bit straight linear SRAMs of 64 entries each,
> rather than 64 entries with 4x64 bits in each row.
> 
> was there a reason why it wasn't done that way?

I'll let Paul comment on the TLB, that's his work, but as for delays,
the biggest issues we have on FPGAs aren't so much logic delays but
wire delays. "wires" in FPGAs are slow and BRAMs impose placement
constraints, especially when you have large (N*64-bit) busses going
in/out. Keep in mind that microwatt targets entry level FPGAs such as
the little Artix in the Arty board with -1 speed grades.

Cheers,
Ben.



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