[OpenPOWER-HDL-Cores] microwatt / libresoc dcache

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed May 12 06:54:32 UTC 2021


On Wednesday, May 12, 2021, Benjamin Herrenschmidt <benh at kernel.crashing.org>
wrote:

>
> > on a practical note, then: i notice that microwatt has 4 "ways" in the
> TLB.
> > perhaps halving that to 2 for resource-constrained FPGAs (and providing
> > it as a compile-time option) would help?
>
> It's a compile time option isn't it ?


let's check

always been a parameter here (since forever), defaults to 4 WAYS:
https://github.com/antonblanchard/microwatt/blob/master/dcache.vhdl#L22

ah that's interesting, WAYS=2 on instantiation:
https://github.com/antonblanchard/microwatt/blob/master/core.vhdl#L22

no evidence of it being selectable in the Makefile though (unless i have
misunderstood or am missing something)
https://github.com/antonblanchard/microwatt/blob/master/Makefile

which makes me curious as to the sky130a modifications by Anton which
briefly whizzed by my eyes and i recall the word "Makefile"

so no, as it stands, not a compile-time option aaiui, but the default is 2
WAYS, 64 SETS.

l.



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