[OpenPOWER-HDL-Cores] load/store conditional

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon May 24 15:30:41 UTC 2021


refs:

* https://en.wikipedia.org/wiki/Load-link/store-conditional
* v3.0B section 4.6.2 p868
* https://github.com/riscv/riscv-isa-manual/blob/master/src/a.tex#L320

paul, hi,

the discussion on wednesday covered a lot of ground, i didn't manage to
successfully communicate my point about LR AX.  i thought it best to follow
up because after reviewing lwarx etc the specification ambiguity i expected
might be there looks like it is.

what appears to be missing is how many instructions are permitted between a
LR and an SC. without this information it imposes a significantly higher
hardware implementation cost and complexity than might at first appear.

for example if we set a limit of only e.g. 2 cache lines worth of
instructions where LR SC sequences will succeed without going into large
repeats, but IBM's POWER9 permits far more than that, all code written for
current GNU/Linux OSes (glibc6, linux kernel) will fail as the RESERVE=1
will expire.

that's if there is even a limit expected (there had better be one! :) )

point being, if there is a limit where RESERVE=1 will expire if an SC does
not occur within a certain number of instructions, it needs to be part of
the spec.

too high a number starts to create huge costs for TLBs etc. because you
can't keep the reservation live without having to request multiple TLB
lookups actually inside the LR SC loop.

and many other things i don't entirely know enough about, yet.

l.



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