[OpenPOWER-HDL-Cores] load/store conditional

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon May 24 19:34:58 UTC 2021


found these, which gives some additional context:
https://elixir.bootlin.com/linux/latest/source/arch/powerpc/include/asm/atomic.h

quick thoughts / reflections, the ATOMIC_OPS(xor) etc are macro-equivalent
to why RV added amoadd, amoand, amoxor etc.

these RV operations (amo*) are what i was referring to that Ariane (Eth
Zurich) actually implemented down in the L2 cache, behind a single
(contended) AXI4 bus.  consequently they can't *be* anything other than
atomic. here's the client-side communication:
https://github.com/openhwgroup/cva6/blob/master/src/cache_subsystem/wt_axi_adapter.sv#L191
now i think about it, i wonder how that would scale? hmm.

all of the other linux kernel ppc macros are very short: maximum of
six/seven instructions, usually 4/5.  they're also very basic.

coming back then to what is in the RV spec:

Floating-point operations and integer
multiply/divide were disallowed to simplify the operating system's
emulation
of these instructions on implementations lacking appropriate hardware
support.

this becomes an issue in Power ISA for Embedded Compliancy where it may be
perfectly reasonable, for saving on context-switching time, to add multiple
SMP cores plus atomic operations.  (we discussed this very scenario on
wednesday, where a single core in FPGA at 50mhz was not quite coping).

if floating point is not implemented, and creates an illegal exception,
that's in the middle of an LR SC, it is going to be challenging.

in Libre-SOC's case, it would be SIMD instructions that, if used in an LRSC
block, could actually end up causing real-world non-hypothetical problems
(because we intend to trap-and-emulate them).

l.





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