[OpenPOWER-HDL-Cores] load/store conditional

Benjamin Herrenschmidt benh at kernel.crashing.org
Tue May 25 01:44:19 UTC 2021


On Mon, 2021-05-24 at 16:30 +0100, Luke Kenneth Casson Leighton wrote:
> refs:
> 
> * https://en.wikipedia.org/wiki/Load-link/store-conditional
> * v3.0B section 4.6.2 p868
> * 
> https://github.com/riscv/riscv-isa-manual/blob/master/src/a.tex#L320
> 
> paul, hi,
> 
> the discussion on wednesday covered a lot of ground, i didn't manage
> to successfully communicate my point about LR AX.  i thought it best
> to follow up because after reviewing lwarx etc the specification
> ambiguity i expected might be there looks like it is.
> 
> what appears to be missing is how many instructions are permitted
> between a LR and an SC. without this information it imposes a
> significantly higher hardware implementation cost and complexity than
> might at first appear.

There is no limit.

> for example if we set a limit of only e.g. 2 cache lines worth of
> instructions where LR SC sequences will succeed without going into
> large repeats, but IBM's POWER9 permits far more than that, all code
> written for current GNU/Linux OSes (glibc6, linux kernel) will fail
> as the RESERVE=1 will expire.
> 
> that's if there is even a limit expected (there had better be one! :)
> )
> 
> point being, if there is a limit where RESERVE=1 will expire if an SC
> does not occur within a certain number of instructions, it needs to
> be part of the spec.

There is no concept of reservations expiring. I don't understand why
your implementation would need such a thing.

> too high a number starts to create huge costs for TLBs etc. because
> you can't keep the reservation live without having to request
> multiple TLB lookups actually inside the LR SC loop.

Why ? The reservation is placed on the physical address after
translation, you just need to hold onto that address and snoop for
collisions.

> and many other things i don't entirely know enough about, yet.
> 
> l.
> 
> 
> 
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