[OpenPOWER-HDL-Cores] practical style / difference between migen and nmigen

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Oct 11 10:00:47 UTC 2021


https://github.com/m-labs/misoc/blob/7c1f614ed3ad9ce0fd3291feccb1e5e4ff65adb3/misoc/interconnect/wishbone.py#L157
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/bus/wb_downconvert.py;h=2fe2a921c4631a54ee67b06e3fab276ecbe36e92;hb=dd84c610a68a556eb532cee133df68c4354dbf32#l4

paul, hi,

on wednesday you asked what the practical difference between migen and
nmigen was, and i remembered i had converted some code (by hand) from
one to the other.

basically, as an extremely crude wrapper around Abstract Syntax Tree,
migen's syntax is barely above the level of lists and tuples.

fsm.act("STATE", list, of, statements) - you have no idea which clock
domain those statements are being added to.

in nmigen: one of the arguments to the FSM is the domain in which you
would like the states to be synchronised.  a good example is here:

https://gitlab.com/Chips4Makers/c4m-jtag/-/blob/master/c4m/nmigen/jtag/tap.py#L54

at a superficial level, migen by relying on lists, tuples, and function call
parameters to provide statements, has an arbitrary layout.  whereas nmigen
uses python constructs such as "with m.If" which forces the developer
to rely on whitespace alignment, consequently making the code much
easier to read.

that said, as i pointed out on #microwatt last week, and also describe here:
http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-October/003832.html

none of these HDLs are *immediately* particularly readable / relate-able
to their underlying gate-level representation, and to that end i found that
for the first five *months* working with nmigen and verilog, compiling
absolutely every single time after every single source code change and
running yosys "show top" was an absolutely essential and critical way
to learn in a concrete what the hell was going on.

hth,

l.


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