[OpenPOWER-HDL-Cores] [Libre-soc-dev] Fwd: [RFC] SVP64 Branches (contd)

Richard Wilbur richard.wilbur at gmail.com
Mon Sep 13 12:15:26 UTC 2021

> On Sep 12, 2021, at 07:28, lkcl <luke.leighton at gmail.com> wrote:
> therefore proper and thorough review with proper feedback and open
> discussion even at an early stage is critical.
> SVP64 is an *extremely* comprehensive ISA that takes considerable
> prior knowledge of 3D GPU and Vector Supercomputer ISAs of the past 50
> years to appreciate why it is the way that it is.
> * Mitch Alsup's MyISA 66000, a comparative peer, has been in draft
> form for a similar timeframe (over 3 years).
> * the author of MRISC32 has been developing the MRISC Vector
> Processing ISA for over 18 months and is still catching up with modern
> and historic Vector Processing techniques and background.
> the absolute last thing anyone needs is a last minute scramble to gain
> sufficient working knowledge in order to be able to assess SVP64 as
> part of a formal OPF ISA WG RFC.  based on how long it has taken to
> develop, this will be flat-out impractical.
> given that SVP64 has taken over 3 years to develop (so far), working
> knowledge of 3D GPU ISAs such as Broadcom VideoCore IV, MALI Midgard,
> Vivante, AMDGPU and Intel GMA, as well as Vector Processing ISAs such
> as Cray, NEC SX Aurora, RVV and Mitch Alsup's MyISA 66000, are
> absolutely essential.

Is there a wiki page with links to documentation where someone could begin to remedy the lack of the “absolutely essential” parts of all the above-mentioned “working knowledge”?  (Or shall I start one?)

How many NDA’s must one sign in order to accomplish the goal of acquiring this “working knowledge”?


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